Synchronous-rectified DC to DC converter with improved current sensing

ABSTRACT

A DC to DC buck pulse width modulator converter circuit includes an input, a high side output and a low side output. A high side switch is electrically connected between a common output node and a voltage supply, and controls a flow of current therethrough dependent upon the high side output. A low side switch is electrically connected between the common output node and ground, and controls a flow of current therethrough dependent upon the low side output. A virtual ground amplifier includes a second input electrically connected to ground. A current feedback resistor is electrically connected intermediate the common output node and a first input of the virtual ground amplifier. A variable impedance component is electrically connected to an output of the virtual ground amplifier and to the first input of the virtual ground amplifier. The impedance of the variable impedance component is varied dependent upon the output of the virtual ground amplifier. A sample and hold circuit is electrically connected intermediate the input of the pulse width modulator converter circuit and the variable impedance component. The sample and hold circuit sources a virtual ground current through the variable impedance component, and samples the virtual ground current.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication Ser. No. 60/151,826, filed Sep. 1, 1999.

This reissue application, U.S. Ser. No. 10/044,506 is the parent ofReissue Continuation application Ser. No. 10/282,753, filed Oct. 29,2002.

FIELD OF THE INVENTION

A synchronous buck DC to DC converter typically employs a pair ofswitches arranged to connect one end of an inductor to either an inputsupply voltage or to ground. The second end of the inductor is attachedto a load. It is well known to use field effect transistors (FET's) asthese switches. Load current flows from the supply through the upper FETand the inductor while that FET is on, and from ground through the lowerFET and the inductor while that FET is on.

It is desirable to sense the value of the load current to performvarious functions such as, for example, to deliberately decrease theoutput voltage as load current increases (i.e., output voltage “droop”),to provide for current limiting or over-current trip to protect the loadand the converter components, and in order to balance the output currentbeing sourced by each channel in a multi-channel or multi-phaseconverter. The load current can be sensed through determining the DCresistance of the inductor and sensing the voltage drop across that DCresistance, or by sensing the voltage drop across an added series senseresistor. The load current can also be detected by sensing the voltagedrop caused by the load current flowing through the upper FET switch.However, each of these methods has their disadvantages. Sensing the loadcurrent by using the DC resistance of the inductor requires adding anR-C filter across the inductor to remove the AC component of thecurrent. Thus, additional components are required and extra costincurred. Adding a series sense resistor also requires an extracomponent, increases cost, and reduces system efficiency. Furthermore,sensing the voltage drop across the drain-to-source resistance of theupper FET when it is conducting has often proven to be impractical,since the “on” time of that switch is typically very short.

Therefore, what is needed in the art is a DC/DC converter with improvedcurrent sensing. Furthermore, what is needed in the art is an apparatusand method which enables the sensing of load current in a DC/DCconverter by sensing the voltage drop across the drain-to-sourceresistance of a switching FET.

Moreover, what is needed in the art is an apparatus and method whichenables sensing and detection of overcurrent in a DC/DC converter.

SUMMARY OF THE INVENTION

The present invention provides a power supply with improved currentsensing.

The invention comprises, in one form thereof, a DC to DC buck pulsewidth modulator converter circuit having an input, a high side outputand a low side output. A high side switch is electrically connectedbetween a common output node and a voltage supply, and controls a flowof current therethrough dependent upon the high side output. A low sideswitch is electrically connected between the common output node andground, and controls a flow of current therethrough dependent upon thelow side output. A virtual ground amplifier includes a second inputelectrically connected to ground. A current feedback resistor iselectrically connected intermediate the common output node and a firstinput of the virtual ground amplifier. A variable impedance component iselectrically connected to an output of the virtual ground amplifier andto the first input of the virtual ground amplifier. The impedance of thevariable impedance component is varied dependent upon the output of thevirtual ground amplifier. A sample and hold circuit is electricallyconnected intermediate the input of the pulse width modulator convertercircuit and the variable impedance component. The sample and holdcircuit sources a virtual ground current through the variable impedancecomponent, and samples the virtual ground current.

An advantage of the DC/DC converter or the present invention is that itprovides an improved method and apparatus to measure the voltage dropacross the drain-to-source resistance of a FET having a very brief “on”time.

Another advantage of the DC/DC converter of the present invention isthat the amount of droop in the output voltage in response to a changein load current is easily manipulated and scaled by selecting anappropriate value for the voltage feedback resistor.

Yet another advantage of the DC/DC converter of the present invention isthat the sensitivity or magnitude of the current limiting or trip iseasily manipulated or scaled by selecting an appropriate value for thevoltage feedback resistor.

A still further advantage of the DC/DC converter of the presentinvention is that a broad range of load current and component values isaccommodated by selecting an appropriate value for the current feedbackresistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned and other features and advantages of this invention,and the manner of attaining them, will become apparent and be betterunderstood by reference to the following description of embodiments ofthe invention in conjunction with the accompanying drawings, wherein:

FIG. 1 is a high-level schematic and functional diagram of oneembodiment of the DC/DC converter of the present invention;

FIG. 2 is a detailed schematic and functional diagram of the DC/DCconverter of FIG. 1;

FIGS. 3a and 3b are timing diagrams illustrating the operation of theDC/DC converter of FIG. 2;

FIG. 4 is a diagram of a node voltage versus load current of the DC/DCconverter of FIG. 2;

FIG. 5 is a schematic of a negative current source for use with theDC/DC converter of FIG. 2; and

FIG. 6 is a detailed schematic of a second embodiment of a DC/DCconverter of the present invention.

Corresponding reference characters indicate corresponding partsthroughout the several views. The exemplifications set out hereinillustrate one preferred embodiment of the invention, in one form, andsuch exemplifications are not to be construed as limiting the scope ofthe invention in any manner.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now to the drawings, and particularly to FIG. 1, there isshown one embodiment of a DC/DC converter of the present invention.DC/DC converter 10 includes low side field effect transistor (FET) 12and high side FET 14. The drain of low side FET 12 is electricallyconnected to the source of high side FET 14 at common output node 16.The drain of high side FET 14 is connected to power supply 18. Thesource of low side FET 12 is electrically connected to ground. Each gateterminal of low side FET 12 and high side FET 14 is electricallyconnected to a respective output (not referenced) of buck convertercircuit 20. Inductor 24 and current feedback resistor 26 are eachelectrically connected to common output node 16, and thus to the drainof FET 12 and source of FET 14. More particularly, inductor 24 iselectrically connected between common output node 16 and load reservoircapacitor 28, and current feedback resistor 26 is electricallyinterconnected between common output node 16 and virtual ground circuitnode 30. A load 32, schematically represented as a resistor, iselectrically connected in parallel with load reservoir capacitor 28.

Virtual ground amplifier 34 has its inverting input 34a electricallyconnected to virtual ground circuit node 30 and its non-inverting input34b connected to ground. Output 34c of virtual ground amplifier 34 iselectrically connected to and drives the gate of FET 36. The source ofFET 36 is electrically connected to virtual ground circuit node 30. Thedrain of FET 36 is electrically connected to sample and hold circuit 38.Thus, as will be apparent to one skilled in the art, virtual groundamplifier 34 and FET 36 are configured to continuously drive virtualground circuit node 30 toward ground potential. With virtual groundcircuit node 30 being continuously driven towards ground potential, theend of current feedback resistor 26 that is connected to circuit node 30will be at ground potential and the end connected to common output node16 will have a negative voltage. This negative voltage at the end ofcurrent feedback resistor 26 that is connected to common output node 16will be equal to the product of output current I_(OUT) and the on-stateresistance that exists between the drain and source (RDS_(ON)) of lowside FET 12. Current I_(SENSE) flows through current feedback resistor26 and has a magnitude determined by the ratio of RDS_(ON) of low sideFET 12 to the value of current feedback resistor 26. Thus, I_(SENSE) isthe product of output current I_(OUT) and the ratio of RDS_(ON) of lowside FET 12 to current feedback resistor 26, and as such isrepresentative of output current I_(OUT). Load current I_(L) is thecurrent flowing through inductor 24 and is substantially equal to outputcurrent I_(OUT) minus I_(SENSE). Typically, since the ratio of RDS_(ON)to the value of current feedback resistor 26 is relatively small,I_(SENSE) is substantially smaller than output current I_(OUT).Therefore, output current I_(OUT) and load current I_(L) will be ofsubstantially similar magnitudes and thus I_(SENSE) will also berepresentative of load current I_(L).

The value of current feedback resistor 26 is selected to provide aconvenient value of current flow for the values of load current I_(L)and/or the value of RDS_(ON) of low side FET 12. Thus, the sensitivityor magnitude of, for example, the voltage droop, current limiting ortrip, and current balancing incorporated into DC/DC converter 10 isscaled by selecting the value of current feedback resistor 26 relativeto the value of RDS_(ON) of low side FET 12. Furthermore, the voltagedrop across RDS_(ON) of low side FET 12, which is usually negative, isaccommodated in DC/DC converter 10 without the need for a negativevoltage supply.

Referring now to FIG. 2, a system control circuit 40 is electricallyconnected to sample and hold circuit 38. As stated hereinabove, thedrain of FET 36 connects to sample and hold circuit 38. The currentsupplied by the source of FET 36 flows from sample and hold circuit 38into the drain of FET 36, out the source of FET 36, and into virtualground circuit node 30. Also flowing into virtual ground circuit node30, from the opposite direction, is I_(SENSE) which, as stated above, isrepresentative of load current I_(L). In order to hold virtual groundcircuit node 30 at ground potential, virtual ground amplifier 34, viaoutput 34c, adjusts the current flowing through FET 36 and into virtualground circuit node 30 to be substantially equal to I_(L SENSE). SinceI_(SENSE) is representative of the load current I_(L), the currentflowing through FET 36 and into virtual ground circuit node 30, ascontrolled by virtual ground amplifier 34 and FET 36, is alsorepresentative of load current I_(L). System control circuit 40periodically issues control signal 40a to sample and hold circuit 38.Control signal 40a is issued when FET 36 is in the on or conductingcondition. In response to control signal 40a, sample and hold circuit 38samples the current flowing through FET 36 when FET 36 is in the oncondition and holds the sampled value. Thus, the sampled value acquiredby sample and hold circuit 38 is also representative of load currentI_(L). Sample and hold circuit 38 issues sample signal 38a which isrepresentative of the sampled value of current flowing through FET 36.

DC/DC converter 10 monitors the voltage V_(OUT) across load 32 throughvoltage feedback resistor 44. Voltage feedback resistor 44 is connectedat one end to load 32 and at the other end to inverting input 46a oferror amplifier 46. V_(FB) is the voltage across voltage feedbackresistor 44. The non-inverting input 46b of error amplifier 46 iselectrically connected to reference voltage supply 48, which provides apredetermined voltage that is substantially equal to the desired outputvoltage of DC/DC converter 10. Error amplifier 46 regulates the voltageat inverting input 46a to be substantially equal to the voltage fromreference voltage supply 48. Since the voltage at inverting input 46a issubstantially equal to the sum of V_(OUT) and V_(FB), error amplifier 46acts to regulate the sum of V_(OUT) and V_(FB) to be substantially equalto the voltage from reference voltage supply 48. Output 46c of erroramplifier 46 is electrically connected to compensation circuit node 50.A feedback path between output 46c and inverting input 46a of erroramplifier 46 includes compensation resistor 52 and compensationcapacitor 54. More particularly, connected to compensation circuit node50 is one end of compensation capacitor 54 which, in turn, is connectedat its other end to compensation resistor 52. Compensation resistor 52,at the end thereof opposite to compensation capacitor 54, is connectedto summing node 56. Compensation resistor 52 and capacitor 54 in thevoltage feedback path provide system stability and control systemresponse.

Sample signal 38a, which is issued by sample and hold circuit 38 and isrepresentative of load current I_(L), is also connected to the invertinginput of error amplifier 46. There is no other path for direct currentat inverting input 46a of error amplifier 46 except through voltagefeedback resistor 44. Thus, the voltage across voltage feedback resistor44, i.e., V_(FB), is modified by sampling signal 38a. As stated above,error amplifier 46 regulates the voltage at its inverting input 46a,which is equal to the sum of V_(OUT) and V_(FB), to be substantiallyequal to the reference voltage supply 48. Thus, for example, as samplingsignal 38a increases V_(FB) increases proportionally and error amplifier46 reduces V_(OUT) to maintain the voltage at inverting input 46a to beequal to reference voltage supply 48. Since sampling signal 38a isrepresentative of load current I_(L), V_(OUT) is in effect modulated inan inversely proportional manner relative to load current I_(L). Thus,as shown in FIG. 4, V_(OUT) is varied or droops dependent at least inpart upon load current I_(L). By selecting the value of feedbackresistor 44, the amount of variation or droop in V_(OUT) relative toload current I_(L) is controlled.

Inverting input 58a of comparator 58 is electrically connected tosawtooth generator 60, and receives therefrom a sawtooth waveform havingpredetermined characteristics. Output 58c of comparator 58 iselectrically connected to set-reset (SR) latch 62. Output 62a of SRlatch 62 is electrically connected to and buffered by driver 64 which,in turn, drives low side FET 12 and high side FET 14. DC/DC converter 10is configured, for example, such that a high-level signal at output 62aof SR latch 62 turns low side FET 12 off and turns on high side FET 14.Sawtooth generator 60 receives sync pulse 66 from system control circuit40. SR latch 62 also receives sync pulse 66.

Error amplifier 46 produces at output 46c a signal that isrepresentative of the actual output voltage V_(OUT) relative to, suchas, for example, subtracted from or added to, the voltage of referencevoltage supply 48, which represents the desired output voltage of DC/DCconverter 10. For example, output 46c of error amplifier 46 produces asignal that is more negative, or increases in a negative direction, asV_(OUT) increases above the voltage of reference voltage supply 48.Conversely, and as a further example, error amplifier 46 produces atoutput 46c a signal having a decreasingly negative magnitude (i.e., amore positive magnitude) as V_(OUT) decreases below the voltage ofreference voltage supply 48. Output 46c of error amplifier 46 iselectrically connected to the non-inverting input of comparator 58.Comparator 58 compares the sawtooth waveform electrically connected toits inverting input 58a with output 46c of error amplifier 46 which iselectrically connected to its noninverting input 58b. Output 58c ofcomparator 58 is active, such as, for example, high during the time thatthe sawtooth waveform generated by sawtooth generator 60 is lesspositive than output 46c of error amplifier 46.

Referring to FIG. 3a, the condition of output voltage V_(OUT) being lessthan the desired output voltage, or less than the voltage of referencevoltage supply 48, is illustrated. Thus, output 46c of error amplifier46 is relatively high, thereby placing a relatively high signal atnoninverting input 58b of comparator 58. At least a substantial portionof the period of the sawtooth waveform will be less positive than therelatively high-level signal present at noninverting input 58b. Output58c of comparator 58 is active, such as, for example, high, during thatsubstantial portion of the period for which the sawtooth waveform has avalue that is less positive than the relatively high signal present atnoninverting input 58b. Thus, the pulse width of output 58c will berelatively wide, or alternatively the active period of output 58c willbe relatively long in duration, when V_(OUT) is less than the voltage ofreference voltage supply 48.

Conversely, and with particular reference to FIG. 3b, output 46c oferror amplifier 46 is relatively low when V_(OUT) is greater than thevoltage of reference voltage supply 48. This condition places arelatively low-level signal at noninverting input 58a of comparator 58.A relatively small portion of the period of the sawtooth waveform willbe less positive than the relatively low-level signal present atnoninverting input 58b. Output 58c of comparator 58 will be activeduring only that relatively small portion, if any, of the period of thesawtooth waveform (e.g., the lowest points or bottom peaks) which isless positive than the relatively low signal at noninverting input 58b.Thus, the pulse width of output 58c will be relatively narrow, oralternatively the active period of output 58c will be relatively shortin duration, when V_(OUT) is greater than the voltage of referencevoltage supply 48.

When output 58c is active, output 62a of SR latch 62 is set, such as,for example, high. Conversely, when output 58c is not active, output 62aof SR latch 62 is reset, such as, for example, low. Thus, when thesawtooth waveform is more positive than the voltage level of referencevoltage supply 48, output 62a of SR latch 62 is reset, i.e., low. Output62a of SR latch 62 is set, i.e., high, when the sawtooth waveform dropsbelow the predetermined voltage. Output 62a of SR latch 62 iselectrically connected to and buffered by driver 64 which, in turn,drives low side FET 12 and high side FET 14. DC/DC converter 10 isconfigured such that, for example, a high or set condition on output 62aof SR latch 62 results in driver 64 turning off low side FET 12 andturning on high side FET 14.

Current tripping or over current protection is provided by overcurrentdetection circuit 70. Overcurrent detection circuit 70 compares thesample signal 38a to a reference current (not shown) and issuesovercurrent signal 70a to system control circuit 40 when sample signal38a exceeds the reference current. System control 40 responds toovercurrent signal 70a by shutting down DC/DC converter 10. Systemcontrol 40 is configured, for example, to restart the operation of DC/DCconverter 10 after a predetermined amount of time.

Negative current source 72 is electrically connected intermediate systemcontrol 40 and virtual ground circuit node 30. Load current I_(L)becomes negative under certain operating conditions, such as, forexample, when load current I_(L) has a low average value and thesawtooth waveform created due to the switching of voltage acrossinductor 24 dips to a negative value. During such operating conditions,i.e., when I_(L) is negative, the voltage at the drain of low side FET12 is positive. The positive voltage on the drain of low side FET 12results in the sourcing of current through resistor 26 and into virtualground circuit node 30, thereby driving virtual ground circuit node 30to a positive potential. Negative current source 72 sourcesI_(PULL DOWN) into virtual ground circuit node 30 in response to signal40 _(N), and thereby maintains virtual ground node 30 at groundpotential under the conditions when I_(L) is negative. Thus, virtualground amplifier 46, variable impedance component 36 and sample and holdcircuit 38 are not required to operate in a bi-directional manner (i.e.,they source current in one direction only) and the need to include anegative voltage supply in DC/DC converter 10 is eliminated.

As best shown in FIG. 5, a negative current source 72 includes switches80, 82 and 84. Each of switches 80, 82 and 84 are, for example, MOStransistors. Current source 86 is a pull down current source, such as,for example, an NMOS mirror, and is electrically connected intermediateground and node 90. Switch 80 is electrically connected intermediatenode 90 and voltage supply 88, and selectively connects node 90 tovoltage supply 88. Capacitor 92 is electrically interconnected betweennode 90 and node 94. Each of switch 82 and 84 have a first sideelectrically connected to node 94. The other side of switch 82 iselectrically connected to ground, while the other side of switch 84 iselectrically connected to virtual ground circuit node 30. Switches 80and 82 are closed and switch 84 is open when the reverse current sourcedby current source 86 is not required to maintain virtual ground circuitnode 30 at ground potential, such as, for example, when low side FET 12is off. The supply voltage of voltage supply 88 is thus stored acrosscapacitor 92, with node 90 having a positive potential and node 94having a negative potential. In order to source pull down current fromcurrent source 86, switches 80 and 82 are each opened and switch 84 isclosed. Thus, I_(PULL DOWN) flows into virtual ground node 30 in thesame direction as normal forward current induced by the voltage drop onlow side FET 12. The addition of current I_(PULL DOWN) maintains virtualground circuit node 30 at ground potential, and is optionally subtractedout later so as not to affect subsequent circuit operation, such as, forexample, the current limit trip point.

In use, and with continued reference to FIGS. 3a and 3b, the sequence ofoperation of DC/DC converter 10 is as follows. Sawtooth generator 60receives sync pulse 66 from system control circuit 40. SR latch 62 alsoreceives sync pulse 66. Sync pulse resets both the sawtooth waveform andoutput 62a of SR latch 62 to low levels. SR latch 62 is configured toreset output 62a based upon sync pulse 66, regardless of the conditionor state of the output of comparator 58. Thus, if the output ofcomparator 58 is, for example, continuously higher than the sawtoothwaveform, output 62a of SR latch 62 will be low during a high level ofsync pulse 66. As shown in FIGS. 3a and 3b at points 200a and 200b,respectively, sync pulse 66 resets the sawtooth waveform generated bysawtooth generator 60 to a low level, and resets output 62a of SR latch62. DC/DC converter 10 is configured such that, for example, when output62a of SR latch 62 is low, high side FET 14 is off and low side FET 12is on. Thus, the resetting of output 62a of SR latch 62 by sync pulse 66turns on low side FET 12. During this time period, i.e., when low sideFET 12 is on, RDS_(ON) of low side FET 12 is measured. At the trailingedge of sync pulse 66, at points 210a and 210b, respectively, thesawtooth waveform begins to slope downward (i.e. has a negative slope).

Referring now particularly to FIG. 3a, the condition of DC/DC converter10 having an output voltage V_(OUT) that is lower than the desired ortarget level is illustrated. Thus, the voltage across load 32 is lowerthan desired. This condition results in output 46c of error amplifier 46having a high level relative to the sawtooth waveform. At point 300a,the leading, or positively sloped, edge of the sawtooth waveform crossesabove the output level of output 46c of error amplifier 46, therebysending output 58c of comparator 58 low. This particular transition inoutput 58c does not affect output 62a of SR latch 62 since sync pulse 66is still active, and thus output 62a remains reset or low.

At point 310a, the trailing, or negatively sloped, edge of the sawtoothwaveform crosses below the output level of output 46c of error amplifier46, thereby sending output 58c of comparator 58 high. This transition inoutput 58c to a high level, in turn, sets output 62a of SR latch 62 highthereby turning high side FET 14 on and turning off low side FET 12. Thehigh level of output 46c relative to the sawtooth waveform results inthe sawtooth waveform dropping below the level of output 46c (at point310a) relatively early in the period of the sawtooth waveform. Thus,points 300a and 310a are relatively close in time, and, therefore, theperiod of time during which low side FET 12 is off is correspondinglybrief. Conversely, the period of time during which high side FET 14 ison and sourcing current is relatively long. Thus, high side FET 14 is onfor a relatively long period of time and sources a greater amount ofcurrent to load 32 when V_(OUT) is less than the desired output voltage.

Referring now FIG. 3b, the condition of DC/DC converter 10 having anoutput voltage that is higher than the desired or target voltage levelis shown. Thus, the voltage across load 32 is greater than desired. Theoutput of error amplifier 46 is therefore low relative to the sawtoothwaveform. At point 300b, the leading, or positively sloped, edge of thesawtooth waveform crosses above the output level of output 46c of erroramplifier 46, thereby sending output 58c of comparator 58 low. Output62a of SR latch 62 has previously been reset by sync pulse 66.

At point 310b, the trailing, or negatively sloped, edge of the sawtoothwaveform crosses below the output level of output 46c of error amplifier46, thereby sending output 58c of comparator 58 high. This transition inoutput 58c to a high level, in turn, sets output 62a of SR latch 62 highthereby turning high side FET 14 on and turning off low side FET 12. Thelow level of output 46c relative to the sawtooth waveform results in thesawtooth waveform dropping below the level of output 46c (at point 310b)relatively late in the period of the sawtooth waveform. Thus, points300a and 310a are separated by a substantially greater amount of timerelative to the situation illustrated in FIG. 3a (i.e., when output 46cis high relative to the saw tooth waveform and/or when V_(OUT) is lessthan the target value). Therefore, the period of time during which lowside FET 12 is on is of a correspondingly longer duration. Conversely,the period of time during which high side FET 14 is on and sourcingcurrent is relatively brief. Therefore high side FET 14 sources a lesseramount of current to load 32 when V_(OUT) is greater than the desiredoutput voltage.

In both cases, i.e., whether the voltage across load 32 is higher orlower than desired, output 62a of SR latch 62 goes low based upon syncpulse 66 rather than dependent upon the relative value of the voltageacross load 32. Output 62a of SR latch 62 remains low at least duringthe duration of sync pulse 66. When output 62a of SR latch 62 is in thelow state, high side FET 14 is in the off condition and low side FET 12is in the on condition, and the voltage drop across RDS_(ON) of low sideFET 12 is sampled and held. However, when low side FET 12 is in the oncondition the direction of load current I_(L) is toward load 32. Thus,load current I_(L) flows from ground through the source to the drain oflow side FET 12 when low side FET 12 is in the on condition. Thisdirection of current flow through low side FET 12 develops a negativevoltage on the drain of low side FET 12. The magnitude of this negativevoltage is the product of I_(L) and the RDS_(ON) of low side FET 12.

In the embodiment shown, the source of low side FET 12 is electricallyconnected to ground. However, it is to be understood that low side FET12 can be alternately configured, such as, for example, having itssource tied through a resistor to ground, and electrically connectingsensing resistor 26 to the source of low side FET 12. The net effect isthe same, and the virtual ground amplifier continues to drive virtualground node 30 to virtual ground. In this alternative configuration,current from Sample and Hold circuit 38 is still representative of loadcurrent I_(L) except the load-current-induced voltage drop across theadded sense resistor is measured rather than the voltage drop acrossRDS_(ON) of low side FET 12. This alternative embodiment is best shownin FIG. 6.

In the embodiment shown, reference voltage supply 48 is described as afixed voltage supply. However, it is to be understood that referencevoltage supply 48 can be alternatively configured, such as, for example,as a bandgap or other fixed voltage source, or may be configured as aDigital to Analog converter or other variable voltage source.

In the embodiment shown, FET 36 is configured as an FET. However, it isto be understood that FET 36 can be alternately configured, such as, forexample, an NPN transistor, with Base substituted for Gate, Emitter forSource, and Collector of Drain.

In the embodiment shown, virtual ground amplifier 34 is configured forcontinuous operation. However, it is to be understood that virtualground amplifier 34 can be alternately configured, such as, for example,an auto-zeroed amplifier or other non-continuously operating amplifier,as it is needed only when low side FET 12 is in the on state.

In the embodiment shown, DC/DC converter 10 is configured such that ahigh-level signal at output 62a of SR latch 62 turns low side FET 12 offand turns on high side FET 14. However, it is to be understood thatDC/DC converter 10 can be alternately configured such that theoperational polarity of FET 12 and FET 14 is reversed.

In the embodiment shown, system control circuit 40 is configured torestart the operation of DC/DC converter 10 after a predetermined amountof time following the detection of an overcurrent condition. However, itis to be understood that system control circuit 40 may be alternatelyconfigured, such as, for example, to issue a visual or audible warningsignal or to completely shut down DC/DC converter 10.

In the embodiment shown, DC/DC converter 10 is configured with inductor24, load capacitor 28 and load 32 connected to node 16. However, it isto be understood that DC/DC converter 10 can be alternately configured,such as, for example, without inductor 24, load capacitor 28 and load 32such that a user, designer, or manufacturer can choose and customizecircuitry attached to node 16 of DC/DC converter 10.

While this invention has been described as having a preferred design,the present invention can be further modified within the spirit andscope of this disclosure. This application is therefore intended tocover any variations, uses, or adaptations of the present inventionusing the general principles disclosed herein. Further, this applicationis intended to cover such departures from the present disclosure as comewithin the known or customary practice in the art to which thisinvention pertains and which fall within the limits of the appendedclaims.

What is claimed is:
 1. A power supply, comprising: a DC to DC buck pulsewidth modulator converter circuit having an input, a high side outputand a low side output; a high side switch electrically connectedintermediate a common output node and a voltage supply, said high sideswitch configured for controlling a flow of current therethroughdependent at least in part upon said high side output; a low side switchelectrically connected intermediate said common output node and ground,said low side switch configured for controlling a flow of currenttherethrough dependent at least in part upon said low side output; avirtual ground amplifier having a first input, a second input and anoutput, said second input electrically connected to ground potential; acurrent feedback resistor electrically connected intermediate saidcommon output node and said first input of said virtual groundamplifier; a variable impedance component electrically connected to saidoutput of said virtual ground amplifier, and to said first input of saidvirtual ground amplifier, said variable impedance component configuredto vary in impedance dependent at least in part upon said output of saidvirtual ground amplifier; and a sample and hold circuit electricallyconnected intermediate said DC to DC buck pulse width modulatorconverter circuit and said variable impedance component, said sample andhold circuit configured to source a virtual ground current through saidvariable impedance component and to sample and hold said virtual groundcurrent.
 2. The power supply of claim 1, further comprising a systemcontrol circuit, said system control circuit electrically coupled tosaid sample and hold circuit, said system control circuit issuing afirst control signal, said sample and hold circuit being configured tosample and hold said virtual ground current in response to said firstcontrol signal, said sample and hold circuit issuing a sample signaldependent at least in part upon said virtual ground current, said systemcontrol circuit selectively activating and deactivating at least one ofsaid high side switch and said low side switch dependent at least inpart upon said sample signal.
 3. The power supply of claim 2, whereinsaid system control circuit issues a sync signal, said sync signalresetting at least one of said high side switch and said low sideswitch.
 4. The power supply of claim 2, further comprising anovercurrent detector circuit electrically coupled to said sample andhold circuit and to said system control circuit, said overcurrentdetector circuit configured for issuing an overcurrent signal when saidsample signal exceeds a predetermined threshold.
 5. The power supply ofclaim 4, wherein said system control circuit is configured for shuttingdown said DC to DC buck pulse width modulator converter circuit inresponse to said overcurrent signal.
 6. The power supply of claim 5,wherein said system control circuit is configured to restart said DC toDC buck pulse width modulator converter circuit a predetermined periodof time after receiving said overcurrent signal.
 7. The power supply ofclaim 2, further comprising a power supply output, a voltage feedbackresistor electrically connected intermediate said power supply outputand said input of said DC to DC buck pulse width modulator convertercircuit.
 8. The power supply of claim 7, wherein said system controlcircuit includes a current mirror, said current mirror sourcing a droopcurrent, said droop current being dependent at least in part upon saidvirtual ground current, said droop current being electrically coupled tosaid input of said DC to DC buck pulse width modulator converter circuitto modify a feedback voltage across said voltage feedback resistor andthereby adjust an output voltage of said power supply dependent at leastin part upon said droop current.
 9. The power supply of claim 1, furthercomprising a negative current source, said system control circuitissuing a second control signal, said second control signal beingelectrically coupled to said negative current source, said negativecurrent source sourcing a negative current in response to said secondcontrol signal, said negative current flowing into said first input ofsaid virtual ground amplifier to thereby connect said current feedbackresistor to ground when current through said current feedback resistoris negative.
 10. The power supply of claim 1, wherein said variableimpedance component comprises one of a field effect transistor and anNPN-type transistor.
 11. The power supply of claim 1 further comprisingan inductor having a first end and a second end, said first endelectrically connected to said common output node, said second endconfigured for being electrically connected to a load.
 12. A method ofsensing an output current in a power supply, said power supplycomprising a DC to DC buck pulse width modulator converter circuithaving an input, a high side output and a low side output, said methodcomprising the steps of: electrically connecting a high side switchintermediate a common output node and a voltage supply, said high sideswitch configured for controlling a flow of current therethroughdependent at least in part upon said high side output; a low side switchelectrically connected intermediate said common output node and ground,said low side switch configured for controlling a flow of currenttherethrough dependent at least in part upon said low side output;directing a sensed current to a virtual ground node, said sensed currentcomprising a known portion of the output current when said low sideswitch is in an on condition, said sensed current flowing into saidvirtual ground node in a first direction; sourcing a virtual groundcurrent into said virtual ground node, said virtual ground currentflowing into said virtual ground node in a second direction, said seconddirection being opposite to said first direction, said virtual groundcurrent being substantially equal to said sensed current and therebycanceling said sensed current at said virtual ground node; and samplingand holding a value of said virtual ground current.
 13. The method ofclaim 12, comprising the further step of selectively activating anddeactivating at least one of said high side switch and said low sideswitch dependent at least in part upon said sampling and holding step.14. The method of claim 12, comprising the further step of selectivelyactivating and deactivating at least one of said high side switch andsaid low side switch on at least one of a periodic and a random basis.15. The method of claim 12, comprising the further steps of: comparingsaid sampled and held value of said virtual ground current to apredetermined maximum limit; and shutting down said power supply whensaid virtual ground current exceeds said predetermined maximum limit.16. The method of claim 15, comprising the further step of restartingsaid power supply a predetermined period of time after said shuttingdown step.
 17. The method of claim 12, comprising the further step ofadjusting an output voltage of said power supply dependent at least inpart upon said sampled and held value of said virtual ground current.18. A power supply, comprising: a DC to DC buck pulse width modulatorconverter circuit having an input, a high side output and a low sideoutput; a high side switch electrically connected intermediate a commonoutput node and a voltage supply, said high side switch configured forcontrolling a flow of current therethrough dependent at least in partupon said high side output; a low side switch electrically connected tosaid common output node and to ground through a sense resistor, said lowside switch configured for controlling a flow of current therethroughdependent at least in part upon said low side output; a virtual groundamplifier having a first input, a second input and an output, saidsecond input electrically connected to ground potential; a currentfeedback resistor electrically connected intermediate said senseresistor and said first input of said virtual ground amplifier; avariable impedance component electrically connected to said output ofsaid virtual ground amplifier, and to said first input of said virtualground amplifier, said variable impedance component configured to varyin impedance dependent at least in part upon said output of said virtualground amplifier; and a sample and hold circuit electrically connectedintermediate said DC to DC buck pulse width modulator converter circuitand said variable impedance component, said sample and hold circuitconfigured to source a virtual ground current through said variableimpedance component and to sample and hold said virtual ground current.19. A control apparatus for DC/DC converter, comprising: a convertercircuit having an input, a high side output adapted to drive a high sidecircuit and a low side output adapted to drive a low side circuit; atleast one current sense node that is adapted to receive a current signalwhen the low side circuit is in an on condition; an amplifier having atleast one input coupled to the at least one current sense node andhaving an output; a variable impedance component coupled to the outputof the amplifier, the variable impedance component configured to vary inimpedance dependent at least in part upon the output of the amplifier;and a sample and hold circuit coupled to the converter circuit, whereinthe sample and hold circuit is configured to sample and hold a currentsourced through the variable impedance component.
 20. The controlapparatus of claim 19, wherein the variable impedance componentcomprises a transistor with an input coupled to the output of theamplifier.
 21. The control apparatus of claim 19, wherein the amplifierhas two inputs, the first input coupled to the current sense node andthe second input coupled to a reference.
 22. The control apparatus ofclaim 19, wherein the variable impedance component comprises atransistor with a first node coupled to the output of the amplifier, asecond node coupled to the current sense node and a third node coupledto the sample and hold circuit.
 23. A power supply, comprising: aconverter circuit having an input, a high side output and a low sideoutput; a high side switch coupled to a common output node, the highside switch configured for controlling a flow of current therethroughdependent at least in part upon the high side output; a low side switchcoupled to the common output node, the low side switch configured forcontrolling a flow of current therethrough dependent at least in partupon the low side output; an amplifier having a first input, a secondinput and an output, the second input coupled to a reference signal; acurrent feedback resistor to provide a signal representative of a loadcurrent to the first input of the amplifier; a variable impedancecomponent coupled to the output of the amplifier, the variable impedancecomponent configured to vary in impedance dependent at least in partupon the output of the amplifier; and a sample and hold circuit coupledto the converter circuit and the variable impedance component, thesample and hold circuit configured to sample and hold a current sourcedthrough the variable impedance component.
 24. The power supply of claim23, wherein the variable impedance component comprises one of a fieldeffect transistor and a bipolar transistor.
 25. The power supply ofclaim 23, further comprising an inductor having a first end and a secondend, the first end coupled to the common output node, the second endconfigured for being coupled to a load.
 26. The power supply of claim23, wherein the variable impedance component further includes a nodethat is coupled to the first input of the amplifier.
 27. A DC/DCconverter, comprising: a control circuit, including: a converter circuithaving an input, a high side output and a low side output; at least onecurrent sense node that is adapted to receive a current signal; anamplifier having at least one input coupled to the at least one currentsense node and having an output; a variable impedance component coupledto the output of the amplifier, the variable impedance componentconfigured to vary in impedance dependent at least in part upon theoutput of the amplifier; and a sample and hold circuit coupled to theinput of the converter circuit, wherein the sample and hold circuit isconfigured to sample and hold a current sourced through the variableimpedance component; a high side switch coupled to a common output node,the high side switch coupled to the high side output of the convertercircuit; a low side switch coupled to the common output node, the lowside switch coupled to the low side output of the converter circuit; anda current sense resistor coupled to the at least one current sense nodeand the common output node.
 28. The DC/DC converter of claim 27, whereinthe variable impedance component comprises a transistor with an inputcoupled to the output of the amplifier.
 29. The DC/DC converter of claim27, wherein the amplifier has two inputs, the first input coupled to thecurrent sense node and the second input coupled to a reference.
 30. TheDC/DC converter of claim 27, wherein the variable impedance componentcomprises a transistor with a first node coupled to the output of theamplifier, a second node coupled to the current sense node and a thirdnode coupled to the sample and hold circuit.
 31. A control apparatus fora DC/DC converter, comprising: a converter circuit having an input, ahigh side output adapted to drive a high side switch and a low sideoutput adapted to drive a low side switch; at least one current sensenode that is adapted to receive a current signal, wherein the currentsignal is representative of a load current of the DC/DC converter; anamplifier having a first input coupled to the at least one current sensenode, a second input coupled to a reference and having an output; avariable impedance component having a first node coupled to the outputof the amplifier, a second node coupled to the at least one currentsense node and a third node, the variable impedance component configuredto vary in impedance dependent at least in part upon the output of theamplifier; and a sample and hold circuit coupled to the convertercircuit and to the third node of the variable impedance component,wherein the sample and hold circuit is configured to sample and hold acurrent sourced through the variable impedance component.
 32. A powersupply, comprising: a DC to DC pulse width modulator converter circuithaving an input, a high side output and a low side output; a high sideswitch electrically connected intermediate a common output node and avoltage supply, the high side switch configured for controlling a flowof current therethrough dependent at least in part upon the high sideoutput; a low side switch electrically connected to the common outputnode and to ground through a sense resistor, the low side switchconfigured for controlling a flow of current therethrough dependent atleast in part upon the low side output; an amplifier having a firstinput, a second input and an output, the second input coupled to areference; a current feedback resistor coupled intermediate the senseresistor and the first input of the amplifier; a variable impedancecomponent coupled to the output of the amplifier and to the first inputof the amplifier, the variable impedance component configured to vary inimpedance dependent at least in part upon the output of the amplifier;and a sample and hold circuit coupled intermediate the converter circuitand the variable impedance component, the sample and hold circuitconfigured to sample and hold a current sourced through the variableimpedance component.
 33. A current sense circuit, comprising: a nodeadapted to receive a signal representative of a load current; anamplifier responsive to the signal received at the node and having anoutput; a variable impedance component, responsive to the output of theamplifier, the variable impedance component providing current to thenode based on the output of the amplifier; and a sample and hold circuitadapted to sample and hold a signal representative of the currentprovided to the node through the variable impedance component.
 34. Acontrol apparatus for a DC/DC converter, comprising: a converter circuithaving an input, a high side output adapted to drive a high side switchand a low side output adapted to drive a low side switch; at least onecurrent sense node that is adapted to receive a current signal, whereinthe current signal is representative of a load current of the DC/DCconverter; an amplifier having a first input coupled to the at least onecurrent sense node, a second input coupled to a reference and having anoutput; a variable impedance component having a first node coupled tothe output of the amplifier, a second node responsive to the currentsignal at the at least one current sense node and a third node, thevariable impedance component configured to vary in impedance dependentat least in part upon the output of the amplifier; and a sample and holdcircuit coupled to the converter circuit and to the third node of thevariable impedance component, wherein the sample and hold circuit isconfigured to sample and hold a current sourced through the variableimpedance component.
 35. A control apparatus for a DC/DC converter,comprising: a converter circuit having an input, a high side outputadapted to drive a high side circuit and a low side output adapted todrive a low side circuit; at least one current sense node that isadapted to receive a current signal when the low side circuit is in anon condition; an amplifier having at least one input coupled to the atleast one current sense node and having an output; a variable impedancecomponent coupled to the output of the amplifier, the variable impedancecomponent configured to vary in impedance dependent at least in partupon the output of the amplifier; and a sample and hold circuit coupledto converter circuit, wherein the sample and hold circuit is configuredto sample and hold a current sourced through the variable impedancecomponent; and wherein the converter circuit includes: a circuit thatcombines the sampled and held current sourced through the variableimpedance component, a signal representative of the output voltage and afirst reference signal to thereby determine an error signal; acomparator, responsive to the error signal, that is adapted to comparethe error signal to a second reference signal to thereby determine acontrol signal; and an output circuit, responsive to the control signalfrom the comparator, the output circuit driving the high side and lowside outputs based at least in part upon the control signal.
 36. Thecontrol apparatus of claim 35, wherein the variable impedance componentcomprises a transistor with an input coupled to the output of theamplifier.
 37. The control apparatus of claim 35, wherein the amplifierhas two inputs, the first input coupled to the current sense node andthe second input coupled to a reference.
 38. The control apparatus ofclaim 35, wherein the variable impedance component comprises atransistor with a first node coupled to the output of the amplifier, asecond node coupled to the current sense node and a third node coupledto the sample and hold circuit.
 39. A power supply, comprising: aconverter circuit having an input, a high side output and a low sideoutput; a high side switch coupled to a common output node, the highside switch configured for controlling a flow of current therethroughdependent at least in part upon the high side output; a low side switchcoupled to the common output node, the low side switch configured forcontrolling a flow of current therethrough dependent at least in partupon the low side output; an amplifier having a first input, a secondinput and an output, the second input coupled to a reference signal; acurrent feedback resistor to provide a signal representative of a loadcurrent to the first input of the amplifier; a variable impedancecomponent coupled to the output of the amplifier, the variable impedancecomponent configured to vary in impedance dependent at least in partupon the output of the amplifier; and a sample and hold circuit coupledto the converter circuit and the variable impedance component, thesample and hold circuit configured to sample and hold a current sourcedthrough the variable impedance component; wherein the converter circuitincludes: an error amplifier adapted to issue an error signal dependentat least in part upon a signal representative of the output voltage, thesampled and held current sourced through the variable impedancecomponent and a first reference signal; a comparator, responsive to theerror signal from the error amplifier, the comparator adapted to issue acomparator signal, the comparator signal based at least in part upon theerror signal and a second reference signal; and an output circuit,responsive to the output signal from the comparator, and adapted toprovide a control signal based at least in part upon the comparatorsignal, where the control signal to drive the low side and high sideswitches.
 40. The power supply of claim 39, wherein the variableimpedance component comprises one of a field effect transistor and abipolar transistor.
 41. The power supply of claim 39, further comprisingan inductor having a first end and a second end, the first end coupledto the common output node, the second end configured for being coupledto a load.
 42. The power supply of claim 39, wherein the variableimpedance component further includes a node that is coupled to the firstinput of the amplifier.